Electronics and Software
Engineering Innovation

FPGA Based Processing Engines

Processing high bandwidth signals in real-time

There are a number of problems to address when processing high bandwidth signals in real time. One of these is the actual data processing speed another is the other is the speed of data communications. The AstroFFT Digital Spectrometer System makes use of the latest generation of Field Programmable Gate Arrays (FPGA's) to perform the real time data processing required. In the case of each AstroFFT processing engine, the input data enters at a rate of about 200 MBytes per second and the 4096 point, 14 bit,  FFT algorithm together with power calculation and integration needs to be performed within 86 microseconds.

FPGA's for Data Processing

A Field Programmable Gate Array (FPGA) consists of a large array of low level electronic gate blocks, each of which can be configured in a number of ways. These gate blocks are interconnected by a large switched matrix. The FPGA's configuration, including the gates interconnection scheme, can be dynamically loaded from a host computer system. This allows a custom hardware design to be loaded, at system run time, to perform a particular task.
Today's FPGA's have relatively slow clock speeds compared with general purpose micro processors, in the order of 300 MHz. However, they are inherently highly parallel, both in terms of processing and internal data communications. It is this parallelism that allows them to perform intensive calculations at a very high speed. The size of FPGA's is increasing all of the time. It is now possible to get devices with up to around 8 million effective low level gates allowing quite complex tasks to be performed.

AstroFFT Processing Engine

The AstroFFT processing engine has been designed for performing the work of a fast real time spectrometer using a FFT algorithm together with power calculator and integrator.

The processing engine has two analogue signal inputs and one digital clock input. A large number of digital I/O lines are available for interconnecting FPGA engines or for other purposes. Each analogue signal is passed through a low pass anti-aliasing filter to a fast 14 bit analogue to digital convertor. The digital signal streams from both analogue to digital convertors are passed through a "glue logic" FPGA to the main processing FPGA. In the case of the AstroFFT system the "glue logic" FPGA's function is to provide master clock selection and remove DC offset from the analogue to digital conversion stages. There are a large number of free gates within this FPGA that could be used to pre-process the data in other ways.
The main processing FPGA is loaded with appropriate "core" firmware to provide the required algorithm. The current supplied algorithms include:

Analogue Mode

The average power of the signal and number of full scale readings are calculated and this information together with the digital signal stream data is sent directly to the host. As the host is unable to keep up with the full data rate, sets of 4096 samples are processed and sent to the host on request.

FFT Mode

A a single digital stream is processed by a 4096 point, 14 bit FFT algorithm and the power of the resulting frequency spectra are integrated over time. The integrated frequency spectra are sent to the host every 0.1 seconds (programmable).


Quadrature FFT mode. The input signals are in quadrature with each other. In this mode one digital stream is sent to the real data inputs and the other data stream is sent to the imaginary inputs of a 4096 point, 14 bit FFT algorithm. The power of the resulting frequency spectra are integrated over time. The integrated frequency spectra are sent to the host every 0.1 seconds (programmable).

Other Uses of FPGA based Data Processing

The FPGA based processing engine can be used in many other application areas where a high bandwidth signal needs to be processed in real time or at a fast rate. In comparison with general computer orientated processing, the coupling of the data source directly to the FPGA removes the I/O bottle neck of the PCI bus. The highly parallel nature of the FPGA allows those algorithms which are parallel by nature, to be efficiently implemented on the hardware available.

FPGA Algorithm Development

The development of algorithms to run efficiently on an FPGA is currently difficult. It requires both software and hardware skills. Normally the algorithm has to be written in a Hardware definition Language, such as Verilog or VHDL. Although 'C' compilers are becoming available, the actual structure of the algorithm has to be written in a way dedicated to hardware used to achieve the high level of parallel performance available.
It is however, possible to make use of "Firmware cores" that have already been developed and integrate them into a more complex system. It is also possible to just pre-process the data on the FPGA leaving the host system to process the reduced bandwidth result using conventional software algorithms.

Typical Uses

  • Processing analogue signal streams of 50 MHz bandwidth.
  • Radio telescope signal processing.
  • Software radio.
  • Processing Sonar signals.
  • Processing Video signals.
  • Complex Audio signal processing.
  • Communications signal processing.
  • Magnetic Nuclear Resonance (MNR) Systems.

Further Details on AstroFFT

Beam Ltd http://www.beam.ltd.uk Tel:  01454 324512
Alpha Data http://www.alphadata.co.uk  
Bristol University http://www.star.bris.ac.uk/coldrick.html